Full Description

Scope

This standard revises and enhances the VHDL language reference manual (LRM) by including a standard Clanguage interface specification; specifications from previously separate, but related, standardsIEEE Std 1164 -1993,1 IEEE Std 1076.2 -1996, and IEEE Std 1076.3-1997; andgeneral language enhancements in the areas of design and verification of electronic systems.

Purpose

The VHDL language was defined for use in the design and documentation of electronics systems. It isrevised to incorporate capabilities that improve the language's usefulness for its intended purpose as well asextend it to address design verification methodologies that have developed in industry. These new designand verification capabilities are required to ensure VHDL remains relevant and valuable for use in electronicsystems design and verification. Incorporation of previously separate, but related standards, simplifies themaintenance of the specifications.

Abstract

Revision Standard - Active.Replaced by IEC 61691-1-1 Ed.2 (2011-05). VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.

Product Details

Published: 01/26/2009 ISBN(s): 9780738158013, 9780738168531 Number of Pages: 0File Size: 1 file , 7 MBRedline File Size:2files, 12 MB Product Code(s): STDSURL95821, STDRL95821, STDSU95821